In the context of CMOS scaling, it is established that below 7-nm CMOS generation, i.e. sub N7, the standard planar/FinFET architecture needs to switch to a vertical type of integration in order to continue scaling. Furthermore, electrostatic control needs to be improved. One option is to develop an architecture based on gate-all-around (GAA) vertical nanowires.
For this purpose, a lower part and an upper part of a vertical semiconductor nanowire is typically surrounded by a dielectric while a central part of the vertical semiconductor nanowire is surrounded by a gate composed of a metal gate electrode separated from the nanowire by a gate dielectric. This central part of the vertical semiconductor nanowire will function as the channel in the FET. The formation of this layer stack (dielectric-gate-dielectric) surrounding the nanowire is particularly challenging.
Two types of approaches can be followed to this end.
The first approach is generally referred to as the “channel last” approach and consists in first forming the layer stack, wherein a sacrificial layer takes the place of the metal layer, then forming a vertical hole through that stack, followed by filling that hole with the semiconductor material of the nanowire to be formed, and finally, replacing the sacrificial layer by a gate composed of a metal layer and a dielectric layer separating the metal layer from the nanowire. The approach of making use of a sacrificial layer is referred to as the “replacement metal gate” (RMG) approach and can be used in both the “channel last” and the “channel first” approach (see below). The “channel last” approach suffers from several drawbacks. One of them being that the nanowire is grown in contact with the walls of the vertical hole. These walls are formed of two different materials, they can hardly be made perfectly regular, and the materials forming them typically presents a lattice mismatch with the material of the nanowire. As a result, the grown nanowire is typically full of defects.
The second approach is generally referred to as the “channel first” approach and consists in first forming the vertical semiconductor nanowire, followed by depositing the stack, layer by layer. The second layer can either be a sacrificial layer as in the first approach or can directly be a dielectric lining followed by a metal layer.
The “channel first” approach comes with its own set of challenges. Already the first dielectric layer is difficult to obtain in a controllable way. The applicant has tried the following approach with mitigated successes (unpublished results): it involved the formation of a hard mask cap on top of the nanowire, followed by the embedding of the nanowire in a thick dielectric layer, followed by the planarization of that dielectric layer, and finally etching the dielectric layer until only the desired bottom portion of the nanowire was covered. The etching step can be performed via a wet etch process or a dry etch process.
For a Si nanowire and a silicon nitride first dielectric layer, a H3PO4 based wet etch at elevated temperature has been tried as it selectively etches the silicon nitride. However, the obtained silicon nitride first layer had an irregular top surface as shown in the focused ion beam image of FIG. 20.
For a Si nanowire and a silicon nitride first dielectric layer, a plasma based dry-etch has been tried but it was slow, could hardly be made selective enough to avoid nanowire consumption, and it also led to an irregular top surface as shown on the focused ion beam image of FIG. 21.
Beside the issue of forming the bottom dielectric layer, the second layer (sacrificial or metal layer) turned out to be even more difficult to control. First, it had to be formed on the already irregular surface of the first dielectric layer. Second, during the formation of the second layer, a thick layer of sacrificial or metal embedding the nanowire was formed, followed by the planarization and etching of that layer. This etching step faced similar problems as faced in the etching of the first layer. In particular, the surface of the second layer (e.g. a metal) after the etch process was rough. Also, the etching tended not to be uniform and to damage the gate junction. Furthermore, the thickness of the second layer was hard to control resulting in an ill-controlled gate length. Needless to say that these problems are repeated for the obtaining of the third layer of the stack.
In addition to the above mentioned drawbacks, the “channel first” approach also suffers from an inability to form well-defined regions along the height of the nanowire. In particular, it might be desirable to have the bottom and top parts of the nanowire (which are surrounded by the first and third layers of the stack) doped, while the middle part of the nanowire (which is surrounded by the second layer of the stack) would remain undoped. Such a succession of doped and undoped regions is difficult to achieve, especially with sharp transitions. Last but not least, in order to have as much control as possible on the gate length, it is desirable that the second layer (i.e. the gate electrode or gate electrode to be) surrounds all the undoped region of the nanowire but only the undoped region of the nanowire in order to have an as much correspondence as possible between the height and vertical position of the undoped channel region of the nanowire with the thickness and vertical position of the sacrificial or metal gate layer. This would permit to have a very well defined gate length.